Key components for implementing SMS4 cryptographic algorithm include a key extension section and an encryption and decryption section. The key extension section and the encryption and decryption section have substantially the same internal structure and processing procedure. The encryption and decryption component mainly includes three parts: a data consignation component, a constant array storage component, and a data conversion component.
The data consignation component mainly includes a generic trigger for consigning data. The data consigned in the data consignation component is constant in a clock cycle. The generic trigger is a data temporary memory which transmits data from its data input to the output of the trigger at a rising or falling edge of a clock and outputs constant data at the output of the trigger at other time.
The constant array storage component is a storage component for storing a constant array. The constant array in the prior art is generally a data array with a width of 32 bits and a depth of 32, which is prepared prior to encryption and decryption processing. Data in the constant array storage component is arranged according to the order of address, e.g. named rk0, rk1, . . . , rk31.
The data conversion component is a component for processing data according to requirements of a cryptographic algorithm, e.g. processing data according to requirements of the national SMS4 cryptographic algorithm. Operations accomplished by the data conversion component include only one synthesis permutation specified by the cryptographic algorithm.
Referring to FIG. 1, a method for encryption and decryption data processing according to the requirements of the SMS4 cryptographic algorithm is described as follows.
1) External Data is Input to the Data Consignation Component 1.
After the external data is input to the data consignation component 1, the data consignation component 1 outputs data from its output. For example, 128-bit external data is divided into 4 32-bit data blocks named A0, A1, A2 and A3 respectively. The data output from the data consignation component is still 128-bit and is 4 32-bit data blocks named a0, a1, a2 and a3 respectively.
2) Data Conversion Processing is Performed.
The data from the output of the data consignation component 1 is input to the data conversion component 2, and data in the first row of constant arrays stored in the constant array storage component 3 is input to the data conversion component 2, for performing data conversion processing. The data a0, a1, a2, a3 from the output of the data consignation component 1 is converted into 128-bit data C0, C1, C2 and C3 via the data conversion component.
3) A Second Data Conversion Processing is Repeated.
The data after the previous data conversion processing is stored in the data consignation component 1 again, then data from the output of the data consignation component 1 is input to the data conversion component 2 again, and data in the next row of the constant arrays stored in the constant array storage component 3 is input to the data conversion component 2, for performing the second data conversion processing.
4) The Second Data Conversion Processing is Repeated to Obtain an Ultimate Data Processing Result.
The data conversion processing is performed on the 128-bit external data for another 30 times. In other words, only if the data conversion processing is performed for 32 times in all, can the ultimate data processing result be obtained.
In the above prior art, the constant array with a width of 32 bits and a depth of 32 is prepared prior to the encryption and decryption processing and the data conversion component performs only one synthesis permutation specified by the cryptographic algorithm, so that the cycle index of the data conversion processing is large. For example, for encrypting 128-bit data, the data conversion processing needs to be performed for at least 32 cycles to obtain the ultimate data processing result.
In addition, the above prior art results in low encryption and decryption efficiency. The encryption and decryption efficiency refers to data volume that is encrypted or decrypted in a unit time. For example, data conversion processing needs to be performed for 32 times for encrypting 128-bit data. At present, the clock frequency in practical application is generally low, so that data volume encrypted in a unit time is small and the efficiency is low. If encryption and decryption efficiency is designated, the clock frequency has to be increased. However, the clock frequency in practical application is difficult to increase, and the practical encryption and decryption efficiency therefore is still low. Also, the increment of the clock frequency will result in difficulty of design and implementation of existing integrated circuits, bad signal integrity, and high design cost. In addition, integrated circuits according to the prior art, if it is applied to a system, may: result in increased cost of printed circuit board, design difficulty of printed circuit board and difficulty of product implementation, and strong interference in the system which may influence normal and high-efficient operations of other devices and apparatus.